The present invention relates to a circuit testing apparatus which is suitable for testing a digital circuit incorporated in a semiconductor integrated circuit element.
FIG. 1 shows the entire arrangement of a conventional circuit testing apparatus. In FIG. 1 reference numeral 100 indicates a device under test (hereinafter referred to as a DUT) such as, for example, an LSI memory or logic circuit. The DUT 100 is supplied with a test pattern signal CP from a pattern generator 200. The pattern generator 200 yields, in addition to the test pattern signal CP, an expected value pattern signal EXP, which is applied to a logical comparison section 400 having a plurality of logic comparison channels. The logical comparison section 400 compares the expected value pattern signal EXP with an output response signal from the DUT 100 and provides a coincidence or noncoincidence signal to an output terminal 500. If necessary, the decided output is stored in a failure analysis memory 600 in preparation for a failure analysis.
In this testing apparatus, level comparison sections 300 of the same number as the number of pins of measuring input channels 301 are provided between the DUT 100 and the logical comparison section 400, although only one level comparison section 300 is shown in FIG. 1 for the sake of brevity. It is determined by the level comparison section 300 whether the level of each output response signal from the DUT 100 is above a specified voltage V.sub.H of an H-logic level or below a specified voltage V.sub.L of an L-logic level. This testing apparatus is adapted for detecting a failure of the DUT 100. Only when the output response signal is above the specified voltage V.sub.H or below the voltage V.sub.L is it considered that a specified logical output level is obtained at the terminal 301, and an L-logic signal is applied to the logical comparison section 400 for logical comparison.
The number of level comparison sections 300 and the number of channels of the logical comparison section 400 are equal to the total number of output terminals of the plurality of DUT's 100 which are measured at the same time. For simultaneously testing a plurality of IC's each having a large number of pins, such as LSI's, several hundreds of sets of level comparison sections 300 and logical comparison channels of the logical comparison section 400 are prepared.
To sort the DUT's 100 according to response speed, it is a general practice in the prior art to provide in the logical comparison section 400 a plurality of signal detectors for detecting the presence or absence of a logical decision output signal, supply them with strobe signals of different timing and determine the presence or absence of the logical decision output signal at the time point of application of the strobe signal. The conventional testing apparatus is arranged, for example, so that it can be determined whether each DUT is high or low in response speed, by detecting whether the logical decision output signal is yielded at the timing of an earlier or later strobe signal after application of a test pattern to the DUT.
FIG. 2 shows an example of such an arrangement. In FIG. 2, reference numeral 300 indicates the level comparison section and 400 the logical comparison section. The level comparison section 300 has two comparators 302 and 303 for one input terminal 301. An output response signal from the DUT 100 (see FIG. 1) to the input terminal is provided to one input terminal of each of the two comparators 302 and 303. The two comparators 302 and 303 are always supplied at the other input terminals with DC voltages V.sub.H and V.sub.L which define normal logical levels H and L, respectively. The comparators 302 and 303 compare the input signal level at the input terminal 301 with the voltages V.sub.H and V.sub.L at the timing of a strobe pulse STRB which is fed to a terminal 306, and hold the comparison results until application of the next strobe pulse. When the input signal level at the terminal 301 is higher than the voltage V.sub.H, the comparator 302 determines that the input signal is at the normal H-logic level, and provides an L-logic signal to an output terminal 304. If the input signal level is not higher than the voltage V.sub.H, then the comparator 302 will provide an H-logic signal to the terminal 304. When the input signal level at the input terminal 301 is lower than the voltage V.sub.L, the comparator 303 decides that the input signal is at the normal L-logic level, and provides the L-logic signal to an output terminal 305. If the input signal level is not lower than the voltage V.sub.L, then the comparator 303 will provide the H-logic signal to the terminal 305. That is to say, when the input signal is at the normal levels H and L, the L-logic signals are provided at the terminals 304 and 305, respectively. When it is decided that the input signal level is intermediate between the voltages V.sub.H and V.sub.L, it is determined that the logical level of the input signal is undefined, and an H-logic signal is provided to both of the terminals 304 and 305. In other words, where the H-logic signals are concurrently provided to the terminals 304 and 305, the output response signal from the DUT does not meet the requirement of either logical level, indicating a failure of the DUT.
In each of channels CH.sub.1, CH.sub.2, CH.sub.3, . . . of the logical comparison section 400 there are provided an H-logic comparator 401H, an L-logic comparator 401L and pluralities of H-logic system signal detectors 402H and 403H and L-logic system signal detectors 402L and 403L for detecting at which timing the logical comparators 401H and 401L yield their outputs. In this example, each system is shown to include two signal detectors.
The logical comparators 401H and 401L can each be formed by a coincidence detect AND gate 4a and a comparison enable AND gate 4b, for instance. The logical comparators 401H and 401L are supplied at their input terminals 404H and 404L with output response signals from the terminals 304 and 305 of the level comparison section 300 and at their input terminals 405H and 405L with expected value signals EXP and EXP and each detect, by the AND gate 4a, coincidence in the H logic between the output response signal and the expected value signal. The coincidence in the H logic indicates that the signal applied to the input terminal 301 of the level comparison section 300 does not have the specified level. Let it be assumed, here, that each AND gate 4a is being supplied with H-logic mask data. Furthermore, a control signal CPE is applied via other input terminals 406H and 406L to the AND gates 4b to permit or inhibit the passage therethrough of the results of logical comparison. Since the level comparator 303 provides the L-logic signal at its output terminal 305 when detecting the L-logic level of the input signal, the expected value signal which is applied to the terminal 405L is an inverted version of the expected value signal EXP which is applied to the terminal 405H, that is, EXP. When detecting coincidence in the H logic between the expected value signal EXP or EXP and the input response signal, the AND gate 4a outputs the H-logic signal.
The logical decision output signals in these H-logic and L-logic systems are provided to data input terminals D of the pairs of signal detectors 402H, 403H and 402L, 403L which are formed by D-type flip-flops, for instance. The signal detectors 402H, 403H and 402L, 403L detect whether the logical decision output signals are present or not at the timing defined by strobe pulses STRB 1 and STRB 2 which are applied to their clock input terminals CK, respectively. Reference numerals 407 and 408 indicate delay elements, by which the strobe pulses STRB 1 and STRB 2 are delayed so that the outputs of the logical comparators 401H and 401L are supplied to the D-type flip-flops 402H, 403H and 402L, 403L a predetermined period of time after the timing of the level comparison in the level comparison section 300, taking into account a delay in the operation of the logical comparators 401H and 401L. The strobe pulses STRB 1 and STRB 2 are provided via an OR gate 409 to the comparators 302 and 303 which constitute the level comparison section 300.
Now, let it be assumed that the strobe pulse STRB 1, for example, is generated earlier than the other strobe pulse STRB 2 by a predetermined time. The level comparators 302 and 303 compare the input signal level with the voltages V.sub.H and V.sub.L, first at the timing of the strobe pulse STRB 1 and hold the results of comparison, which are provided to the flip-flops 402H and 402L by the strobe pulse STRB 1 delayed by the delay element 407. Next, the level comparators 302 and 303 perform the level comparison at the timing of the strobe pulse STRB 2 and the results of comparison are provided to the flip-flops 403H and 403L by the strobe pulse STRB 2 similarly delayed by the delay element 408. The logical test results thus provided to the flip-flops 402H, 403H, 402L and 403L are written via terminals 411H, 412H, 411L and 412L into corresponding storage areas of the failure analysis memory 600 shown in FIG. 1. Though not shown, in the actual testing apparatus D-type flip-flops are provided for writing the outputs of the flip-flops 402H, 403H, 402L and 403L in synchronism with the operating clock of the testing apparatus. Of such synchronized output data, corresponding outputs of the H-logic and L-logic systems are ANDed by AND circuits (not shown), and when the AND is H-logic, it is determined that the response output of the DUT is a failure. However, the circuits associated with this are not related to the subject matter of the present invention, and hence are not shown.
With the provision of the plurality of signal detectors 402H, 403H, 402L and 403L, it is possible to determine whether the operation of the DUT 100 is normal or not and to classify the response speed distribution of many DUT's 100 into a plurality of regions. Now, assume that the timing for generating the strobe pulses STRB 1 and STRB 2 is set to T.sub.1 and T.sub.2. By testing the DUT's 100 on the basis of the timing T.sub.1 and T.sub.2, they can be classified into a high response region A, a normal response speed region B and a low response speed region C as shown in FIG. 3. For example, in the case of the H-logic system, when the logical determination output signals loaded into the flip-flops 402H and 403H by the strobe pulses STRB 1 and STRB 2 are both H-level, it is seen that the DUT 100 belongs to the high response speed region A. When the logical determination output signals loaded into the flip-flops 402H and 403H by the strobe pulses STRB 1 and STRB 2 are L-level and H-level, respectively, it is seen that the DUT 100 belongs to the normal response speed region B. When the logical determination output signals loaded into the flip-flops 402H and 403H are both L-level, it is seen that the DUT 100 belongs to the low response speed region C. This classification can be performed using logical signals which are provided at the output terminals 411H and 412H. A similar test can also be made for the L-logic system.
In the arrangement shown in FIG. 2, the two strobe pulses STRB 1 and STRB 2 of different timing are superimposed on each other by the OR gate 409 into one time series signal, which is applied to the level comparators 302 and 303. Therefore, the time interval between the strobe pulses STRB 1 and STRB 2 is limited to 10 nanoseconds or more owing to the circuit structure of the OR gate 409. If they are generated at a shorter time interval, they will combine into a single pulse, making it impossible to detect the rise and fall of the response output signal belonging to the region B depicted in FIG. 3.
Recently storage elements have been rendered high-speed and some of them rise in as short a time as 10 to 25 nanoseconds. For testing such quick response type elements, the two strobe pulses STRB 1 and STRB 2 must be generated at time intervals of 2 to 5 nanoseconds. However, the conventional method cannot afford such a reduction of the time interval between the strobe pulses. Therefore, quick response type memories cannot be classified by one test for each memory and at least two tests must be made for each memory while changing the setting of the timing for generating the strobe pulses.
On the other hand, when some of the DUT's 100 output signals of periods shorter than the operation cycle of the testing apparatus, they must be tested in addition to the test for classifying them according to their response speed. The prior art employs a pin multiplex system for such a test.
According to the pin multiplex system, as shown in FIG. 4, the output signal of the level comparison section 300 is applied to the logical comparators 401 provided in a plurality of channels, for example, two channels CH.sub.1 and CH.sub.2, and in the plurality of logical comparators 401 the output signal is subjected to the logical comparison with expected value signals EXP 1 and EXP 2 of a normal cycle speed. The results of comparison are provided to the signal detectors 402 provided in the respective channels CH.sub.1 and CH.sub.2, thereby detecting the presence or absence of signals at the timing of the strobe pulses STRB 1 and STRB 2. While in FIG. 4 the logical comparison section 400 is shown to include the channels of the H-logic system alone, the L-logic system is also provided in practice as is the case with FIG. 2.
According to the pin multiplex system, assuming that the DUT 100 outputs response signals P.sub.A, P.sub.B, P.sub.C, P.sub.D, . . . which vary, for instance, twice in one test cycle T.sub.M as depicted in FIG. 5A, the output response signals P.sub.A, P.sub.B, P.sub.C, P.sub.D, . . . are applied via the level comparison section 300 to the logical comparators 401 provided in the two channels CH.sub.1 and CH.sub.2.
The logical comparators 401 are supplied at one input with expected value signals EXP.sub.11, EXP.sub.12, . . . and EXP.sub.21, EXP.sub.22, . . . which vary at a normal speed (i.e. with the period T.sub.M) as shown in FIGS. 5D and 5E, respectively. Further, the logical comparators 401 are supplied at another input with signals CPE 1 and CPE 2 which control whether or not to perform the logical comparison. The output response signals P.sub.A, P.sub.B, P.sub.C, P.sub.D, . . . of the speed twice higher than the normal speed and the expected value signals EXP.sub.11, EXP.sub.12, . . . and EXP.sub.21, EXP.sub.22, . . . in the two systems are compared by the logical comparators 401 in the different channels. The results of comparison are provided to the signal detectors 402 in the respective channels.
The signal detectors 402 are supplied with the strobe pulses STRB 1 and STRB 2 depicted in FIGS. 5B and 5C, respectively. The signal detectors 402 provide at an output terminal 411 of the channel CH.sub.1 such logical decision output signals P.sub.AA, P.sub.CC, P.sub.EE, . . . as shown in FIG. 5F, and at an output terminal 411 of the channel CH.sub.2 such logical decision output signals P.sub.BB, P.sub.DD, P.sub.FF, . . . as depicted in FIG. 5G. Thus, the logical decision output signals P.sub.AA, P.sub.CC, P.sub.EE, . . . and P.sub.BB, P.sub.DD, P.sub.FF, . . . are of the normal speed of the testing apparatus and can be written into the failure analysis memory and utilized for various analyses.
Since the pin multiplex system utilizes the plurality of channels CH.sub.1 and CH.sub.2 for the output response signal from one output terminal of the DUT, this system is defective in that the number of channels used needs to be a multiple of the number of operation cycles of the DUT relative to that of the testing apparatus. That is, it is necessary to provide channels of a number at least twice that of output terminals of the DUT; this inevitably enlarges the scale of the apparatus and raises its manufacturing costs.
Furthermore, in a failure analysis of memories, for example, the situation occasionally arises where it would be desirable to sort individual memory cells according to varied test conditions. For instance, there is the case where it is desirable to sort the cells according to whether or not they meet the condition of an access time b, the cells which meet the condition of the access time b but do not meet the condition of an access time c (where c &lt;b), and the cells which meet the condition of the access time c but do not meet the condition of an access time d (where d &lt;c).
In such sorting, if the access times b, c and d are, for example, 35, 30 and 25 nanoseconds, respectively, then the conventional testing apparatus shown in FIG. 2 cannot use the strobe pulses STRB 1 and STRB 2 at the time interval of 5 nanoseconds. It is therefore necessary to perform logical comparisons test by use of the strobe pulse STRB 1 alone, without using the strobe pulse STRB 2, and conduct the tests one by one while changing the timing of the strobe pulse STRB 1 for each of the test conditions. Accordingly, in the prior art the test must be carried out four times as described below in connection with one channel.